The present invention relates to a voltage comparator circuit and, more particularly, to a voltage comparator circuit which is suitable for use in an A/D (analog/digital) converter.
Prior voltage comparator circuits have been disclosed in such literature as, "Monolithic Expandable 6 bit 20 MHz CMOS/SOS A/D Converter", 1979, IEEE Journal of Solid-State Circuits, Vol. SC-14, U.S. Pat. No. 3,676,702, and the like.
A conventional voltage comparator circuit will now be described, with reference to FIGS. 1 to 5. FIG. 1 is a circuit diagram showing a conventional voltage comparator circuit. FIG. 2 shows waveforms of clocks .phi..sub.1 and .phi..sub.2 for controlling the operation of the voltage comparator circuit of FIG. 1.
In FIG. 1, when .phi..sub.1 =V.sub.SS ("logic 0") and .phi..sub.2 =V.sub.DD ("logic 1"), a transfer gate 1 is opened by clocks .phi..sub.1 and .phi..sub.2, and a voltage V.sub.c of an output node 2 thereof an input signal V.sub.in2. In other words, V.sub.c =V.sub.in2. A transfer gate is constituted by an N-channel MOS transistor connected in parallel with a Pchannel MOS connector transistor. A transistor gate 4 composed of a P-channel MOS transistor and an N-channel MOS transistor is also similarly opened by clocks .phi..sub.1 and .phi..sub.2, and an output voltage V.sub.out on output terminal 7 of an amplifier 6 is fed back to a node 5 of transfer gate 4. Amplifier 6 is composed of a P-channel MOS transistor and an N-channel MOS transistor which are serially connected between V.sub.DD and V.sub.SS.
FIG. 3 is a characteristic diagram of input and output voltages of amplifier 6. In FIG. 3, the abscissa indicates an input voltage V.sub.in of the amplifier, and the ordinate represents an output voltage V.sub.out thereof. The input/output characteristics of the amplifier are as shown by a curve A. The DC feedback characteristic, which is derived when the input and output are short-circuited, is as shown by a curve B. Therefore, a voltage V.sub.in at node 5 becomes the voltage at the point where curves A and B cross, in FIG. 3. The voltage at the intersect point of curves A and B is defined as the operating point voltage V.sub.op of amplifier 6; i.e., V.sub.in =V.sub.out =V.sub.op.
Next, when clock .phi..sub.1 =V.sub.DD ("logic 1") and .phi..sub.2 =V.sub.SS ("logic 0"), transfer gates 1 and 4 are closed, and a transfer gate 8 is opened, so that an input voltage V.sub.inl is input and voltage V.sub.c at node 2 becomes V.sub.c =V.sub.inl. In this case, since the potential difference across a capacitor 10 does not change potential V.sub.in at node 5 is changed only by the amount of potential change at node 2, i.e., only by the amount of (V.sub.inl -V.sub.in2). Therefore, potential V.sub.in at node 5 becomes EQU V.sub.in =(V.sub.in1 -V.sub.in2)+V.sub.op
Assuming that gain K of amplifier 6 is less than "zero", output voltage V.sub.out becomes EQU V.sub.out =K.multidot.(V.sub.in1 -V.sub.in2)+V.sub.op
In order to increase the operation speed and the input sensitivity of the voltage comparator circuit, it is required that the amplifier has a high voltage gain K and a low output impedance Zout. Voltage gain K and output impedance Zout of a conventional amplifier will now be considered.
FIG. 4 is a circuit equivalent to amplifier circuit 6 of the comparator of FIG. 1. FIG. 5 shows V.sub.DS -I.sub.DS characteristics (V.sub.DS : drain-source voltage, I.sub.DS : drain-source current) of the P-channel type MOS transistor and N-channel type MOS transistor which constitute amplifier 6.
From the equivalent circuit shown in FIG. 4, voltage gain K is expressed as follows: EQU K=gm.multidot.r.sub.dst
where, gm=gmN+gmP and ##EQU1##
Output impedance Z.sub.out becomes EQU Z.sub.out =r.sub.dst
where, gm is a mutual conductance, gmN is a natural conductance of the N-channel MOS transistor, gmP is a mutual conductance of the P-channel MOS transistor, r.sub.dst is a saturation drain resistance, r.sub.dsN is a saturation drain resistance of the N-channel MOS transistor, and r.sub.dsP is a saturation drain resistance of the P-channel MOS transistor.
From FIG. 5, it will be understood that r.sub.dsN and r.sub.dsP are expressed as follows: EQU r.sub.dsN =.DELTA.V.sub.N /.DELTA.I.sub.N EQU r.sub.dsP =.DELTA.V.sub.P /.DELTA.I.sub.P
.DELTA.V.sub.N and .DELTA.V.sub.P denote microchanges in the amount of the voltages which are applied between the source and drain of each of the N-channel and P-channel MOS transistors, respectively. .DELTA.I.sub.N and .DELTA.I.sub.P denote microchanges in the amount of the currents which flow through the N-channel and P-channel MOS transistors corresponding to .DELTA.V.sub.N and .DELTA.V.sub.P, respectively. When the channel lengths of the P-channel and N-channel MOS transistors are reduced, .DELTA.V.sub.P /.DELTA.I.sub.P and .DELTA.V.sub.N /.DELTA.I.sub.N decrease, as does output impedance Z.sub.out. However, voltage gain K is also reduced. On the other hand, when the gate lengths are increased, voltage gain K increases, and so does output impedance Z.sub.out.
As is mentioned above, in the amplifier used in the conventional example of FIG. 1, when the gain of the amplifier is increased, the output impedance is also increased. On the other hand, when the output impedance of the amplifier is decreased, the gain is also decreased. Consequently, a voltage comparator circuit having high speed and high input sensitivity cannot easily be realized.